Conventionally, a data processing apparatus is known that uses a sharing arbitration circuit. The sharing arbitration circuit can arbitrate the sharing of a semiconductor memory circuit among multiple data processing circuits. Examples of such conventional data processing apparatuses are shown in Japanese Patent Publication JP 06-83780A, JP 11-272632A, and JP 2000-298652A.
Referring to FIG. 4, a conventional example of a data processing apparatus described above is shown, and designated by the general reference character 100. A data processing apparatus 100 can include a synchronous dynamic random access memory (SDRAM) 101 provided as a semiconductor memory device, two data processing circuits 102, constituted by one-chip microcomputers, an arbiter circuit 103 operating as a sharing arbitration circuit, and a bus control circuit 104.
The SDRAM 101 and two data processing circuits 102 are connected through system buses 105 having bus controller 104 at the center. Data processing circuits 102 are connected with arbiter circuit 103 through dedicated signal lines 106. Arbiter circuit 103 is connected with bus control circuit 104 through a dedicated signal line 107.
A requester circuit 108 and interface (I/F) circuit 109 are built into each data processing circuit 102. Requester circuits 108 are in signal communication with arbiter circuit 103, and I/F circuits are in signal communication with SDRAM 101 through system bus 105. A clock oscillation circuit (not shown) is provided to data processing apparatus 100 independently of the arrangement described above, and this clock oscillation circuit supplies the individual parts of the data processing apparatus 100 with a common clock signal.
In the conventional data processing apparatus 100 described above, the SDRAM 101 executes data reads and data writes in response to command signals and address signals received external to the SDRAM 101 by way of system bus 105. Such operations are conducted in synchronism with the clock signal received externally from the clock oscillation circuit.
It is noted that in the conventional example shown in FIG. 4, because two data processing circuits 102 are connected to a single SDRAM 101, it is necessary to selectively connect one data processing circuit 102 with the SDRAM 101 according to a control operation. In particular, in the data processing apparatus 100 of FIG. 4, arbiter circuit 103 controls the operational state of the two data processing circuits 102 and controls the operation of bus control circuit 104 to selectively connect one of the two data processing circuits 102 with the SDRAM 101.
In the conventional data processing apparatus 100 described above, because bus control circuit 104, controlled by the arbiter circuit 103, selectively connects one of the two data processing circuits 102 with the SDRAM 101, it is possible for the two data processing circuits 102 to share the SDRAM 101.
Thus, bus control circuit 104 is conventionally considered necessary for switching a connection between data processing circuits 102 and a shared single SDRAM 101. However, such a circuit increases overall circuit scale (e.g., size). Further, the bus control circuit 104 can decrease overall operating speed, as such a circuit introduces a switching delay into data access operations.
To address the above drawbacks of the conventional approach, one may consider eliminating the bus control circuit 104 and directly connecting the data processing circuits 102 and SDRAM 101 by way of system bus 105. Operations of the multiple data processing circuits 102 could then be arbitrated according to arbiter circuit 103. However, such an approach may be difficult to implement.
For example, when a double data rate (DDR)—SDRAM is used as a semiconductor memory circuit, the DDR-SDRAM operates at a high speed in synchronism with the rise and fall of a clock signal. Thus, it is necessary to change a control signal supplied form the data processing circuits to the DDR-SDRAM from a high electric potential (such as VDD) to a low electric potential (such as GND) with respect to center reference level (such as ½ VDD).
In such a proposed conventional arrangement, when the supply of a control signal is interrupted by switching of the data processing circuit currently controlling the DDR-SDRAM, the DDR-SDRAM can misinterpret the undefined state of the control signal as high or low. This can result in the malfunction of the DDR-SDRAM. Thus, in a data processing apparatus that shares a DDR-SDRAM among multiple data processing circuits 102, because it may not be possible to eliminate a bus control circuit 104, such a data processing apparatus suffers from increased circuit size. At that same time, as noted previously, response speed decreases due to the presence of the bus control circuit 104.
In light of the above, it would be desirable to arrive at some way of enabling a semiconductor memory circuit to be shared among multiple data processing circuits without the use of a bus control circuit. At the same time, such a solution should not suffer from the potential malfunctions that can occur in conventional arrangements.